DESIGN AND ANALYSIS OF LOW POWER MBFF USING DIFFERENT LOGICS

---

Amgoth Laxman, Dr. N. Siva Sankara Reddy, Dr. B. Rajendra Naik

Vol 18, No 7 ( 2023 )   |  Licensing: CC 4.0   |   Pg no: 197-206   |   Published on: 27-07-2023

---

Abstract
Power dissipation is responsible for high-performance digital systems in the sub-micron range. As a result, power inside small systems is critical. This study analyzes four various types of MBFF employing regular CMOS, transmission gates, pass transistors, and GDI gates. According to simulation results, the recommended GDI-based MBFF has the lowest PDP. When compared to others, PTL requires fewer transistors to build an MBFF. T-SPICE is used to model circuits with 45 nm manufacturing technology. The simulation is carried out in terms of delay, power, and Power Delay Product (PDP) for supply voltages of 0.8 V and 1.2 V.

Keywords:
#

---

Download Full Article PDF